Embedded Files
Course Outline:
Course Outline:
Instructor:
Instructor:
Chen-Yi Lee, Vice President of National Yang Ming Chiao Tung University
Office: ED538
Tel: 03-5731849
Mail: cylee@si2lab.org
Senior Teaching Assistant:
Senior Teaching Assistant:
Lin-Hung Lai, Ph.D. Candidate of National Yang Ming Chiao Tung University
Office: ED430
Tel: 03-5712121 #54238
Mail: lhlai@ieee.org
Prerequisites:
Prerequisites:
Introduction to VLSI, Logic Design, Digital System Design, Computer Organization (Opt)
Course Objectives:
Course Objectives:
This course aims to convey the senior and graudated EE students techniques to design the VLSI chips using state-of-the-art CAD tools. In addition to learning CAD tools for performance-driven and cost effective IC designs, a top-down design flow and related environment will also be addressed. Upon completion of the course, the student will be able to design the integrated circuits and systems based on standard cell library as well as full-custom layout approaches. As such he/she will be able to work in a team of designers or stand alone.
Teaching Assistant Group:
Teaching Assistant Group:
Lin-Hung Lai, Ph.D. Candidate, lhlai@ieee.org
Wen-Yue Lin, Ph.D. Student, kenlin.eed06@nctu.edu.tw
Wang-Hai Feng, Master Student, whf87tww@gmail.com
Huan-Jung Lee, Master Student, alexli1205.ee09g@nctu.edu.tw
Chih-Wei, Peng, Master Student, epeng.ee06@nycu.edu.tw
Shao-Wen Zheng, Master Student, shaowen0213@gmail.com
Yi-Chin Wang, Master Student, echinwang861025@gmail.com
Lecture:
Lecture:
3EF (13:30 ~ 15:30, Wednesday) @ ED415
1EF (13:30 ~ 15:30, Monday) @ ED415 for Lab1~Lab4
Grading Policy:
Grading Policy:
Weekly Lab Exercise x 12 (60%)
Midterm Project (10%)
Midterm Exam (6%)
Online Test (8%)
Final Project (10%)
Final Exam (6%)
Bonus (Formal Verification) (5%)
Course Schedule & Material:
Course Schedule & Material:
All contents below keep confidential, do not separate and abused
And academic usage only, no commercial purpose
Materials belong to National Yang Ming Chiao Tung University (NYCU)
System Integration and Silicon Implementation (Si2) Lab.
© 2021,NYCU Si2 Lab. All rights reserved.
Week1 (2021.09.15)
Lab00 Introduction + Environment Setting
Lecturer: Lin-Hung Lai
Week2 (2021.09.21)
Lab01 Cell Based Design & Verilog Combinational Circuit Programming
Lecturer: Lin-Hung Lai
Lab
Week3 (2021.09.29)
Lab02 Finite State Machine & Verilog Sequential Circuit Programming
Lecturer: Yi-Chin Wang
Lab
Week4 (2021.10.05)
Lab03 Verification & Simulation & Verilog Test Bench Programming
Lecturer: Wen-Yue Lin
Lab
Week5 (2021.10.12)
Lab04 Sequential Circuit Design II (STA + Pipeline)
Lecturer: Wang-Hai Feng
Lab
Week6 (2021.10.19)
Lab05 Memory & Coding Style (Memory Compiler + SuperLint)
Lecturer: Shao-Wen Zheng
Lab
Week7 (2021.10.26)
Lab06 Synthesis Methodology (Design Compiler + IP Design)
Lecturer: Huan-Jung Lee
Lab
Week8 (2021.11.02)
Midterm Exam + Online Test + Midterm Project
Midterm Exam: Link
Online Test
Midterm Project
Week9 (2021.11.09)
ICLab Lab07 Timing: Cross Clock Domain + Synthesis Static Time Analysis
Lecturer: Wang-Hai Feng
Lab
Week10 (2021.11.16)
ICLab Lab08 Power: Low Power Design + Sequential Equivalent Checking
Lecturer: Shao-Wen Zheng
Lab
Week11 (2021.11.23)
Lab09 System Verilog I (Design)
Lecturer: Chih-Wei, Peng
Lab
Week12 (2021.11.30)
Lab10 System Verilog II (Verification)
Lecturer: Chih-Wei, Peng
Lab
Week14 (2021.12.14)
Lab11 APR I : From RTL to GDSII
Lecturer: Huan-Jung Lee
Lab
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