Special Topic
Frequency Based Capacitor Sensor
Embedded Files
Advisor:
Advisor:
Prof. Chen-Yi Lee, Vice President of National Yang Ming Chiao Tung University
Office: ED538
E-mail: cylee@si2lab.org
Si2 Official Website: www.si2lab.org
Recent Meeting:
Recent Meeting:
Meeting
Bio-weekly Meeting
Next meeting: 07/14 18:00 @ Google Meeting
Member List:
Member List:
Topic Leader
Lin-Hung Lai | Ph.D.
Office: ED430 | EIC213
E-mail: lhlai@ieee.org
Group #1 (Frequency Based Capacitor Sensor)
蔡宗儒 | Undergraduate | FBCS
謝品軒 | Undergraduate | FBCS
蕭邦原 | Undergraduate | FBCS
Group #2 (HD Capacitance Sensing System on BioFPGA)
洪崇恩 | Undergraduate | Ethernet
蘇子傑 | Undergraduate | Electrical Characteristics
Slides Requirement:
Slides Requirement:
Each one should be at least 5 slides, within 30 mins for all.
Use Google slides for online editing
Imagine you are a teacher, you would like to teach others what you understand.
Try to find out related pictures/tables to illustrate a complex idea.
Please must attach the reference/resources within your slides.
Please must attach the page numbers to your slides.
Slides can be some study record for yourself, it's helpful when you need them in the future.
Good luck and enjoy it :))
G1 Progress:
G1 Progress:
04/07 (Thu.):
FBCS Paper Presenting + PLL Intro.
05/05 (Thu.):
IC Intro. and Discussion
05/12 (Thu.):
ADPLL Paper Presenting (Paper)
Why do we need a PLL?
What's the difference between Analog and Digital?
What's the factor used to judge the performance of ADPLL?
What is jitter and type of jitters?
What's the basic component of ADPLL?
What's the technique used in the proposed ADPLL?
What are the pro and cons of such method?
Can we prevent these cons or any better approach?
05/19 (Thu.):
Hspice Introduction & Implementation
06/02 (Thu.):
Layout Introduction & Implementation
06/29 (Wed.):
1 bit FA and INV Layout Discussion
07/14 (Thu.):
4 bit FA and .vec Layout Discussion
G2 Progress:
G2 Progress:
07/14 (Thu.):
Paper Discussion
Google Sites
Report abuse